This invention relates to a word oriented processing system. Such a system contains a processing unit and a memory. The invention also relates to a ferroelectric memory device suitable for use in such a processing system.
From European patent application No EP-A 0359404 which corresponds to U.S. Pat. No. 4,888,733 (Dec. 19, 1989), a ferroelectric memory is known which contains ferroelectric capacitors containing ferroelectric material between their plates. A bit of information is represented in this ferroelectric memory as an amount of remanent polarization of the ferroelectric material. Reading and writing of such a bit involves supplying a voltage pulse across the plates of the capacitor. This pulse is supplied to the memory via a bitline connection and a plateline connection.
The known memory comprises memory units organized in rows and columns. The units in a column are connected in common to a bitline and a plateline. In order to access only the capacitor in one of these units at a time, the known memory provides for a row select line. By using this row select line, access may be restricted to a unit from one row at a time by the selective activation of first and second switching elements in the units in one row.
The abovementioned publication teaches the use of two switching elements in a unit, connected respectively between the bitline and a first plate of the capacitor and the plateline and a second plate of the capacitor. The use of two switching elements prevents both that a pulse current occurs via the ferroelectric capacitor when the unit is not selected, and also that a pulse voltage is supplied to either plate of the ferroelectric capacitor; no matter whether such a pulse occurs on the plateline connection or on the bitline connection of the unit.
This substantially prevents parasitic disturbance of the polarization on the capacitors in unselected units. However, the prior art memory has the disadvantage that it achieves this effect by using twice as many switching elements as there are capacitors, which constitutes a large amount of overhead for a memory circuit.